A Power Adaptive Low Power Low Noise Band-pass Auto-zeroing CMOS Amplifier for Biomedical Implants

A Power Adaptive Low Power Low Noise Band-pass Auto-zeroing CMOS Amplifier for Biomedical Implants

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Two micro-power, low-noise, bandpass sense amplifiers for biomedical implants are presented. Operating at low frequency, both amplifiers are fully integrated without any external passive components. Low-frequency noise and offset are reduced through autozeroing technique. Autozeroing frequency and noise bandwidth are optimized to reduce noise folding. Subthreshold operation is utilized in all input pair transistors to reduce power consumption and increase trans-conductance efficiency. The impact of mismatch from transistors in weak inversion are measured and the proposed amplifiers are proved to function correctly against these mismatch issues. The first generation sense amplifier consists of a variable gain amplifier as the first stage, a low-Gm high-pass filter as the second stage, and a low-pass Gm-C amplifier as the last stage. The low-Gm OTA (Operational Trans-conductance Amplifier) is realized with a current division technique. A cross-couple parallel pair of source degeneration transistors is utilized to increase the linearity crucial to neural spike detection. The design is realized in TSMC 0.18um CMOS process. It achieved 600uV input offset, a variable gain from 42dB to 0dB, and 50 to 900 Hz bandwidth while occupying 0.245mm2 area. The total circuit consumes 26uW in a 1.8V power supply; the input referred noise is estimated to be 5.6uV rms. A power-adaptive, bandpass second generation amplifier is reported as the improved design. The amplifier consists of a novel variable gain amplifier, and a 2nd order Gm-C filter by cascading two identical low-Gm high-pass filter and low-pass Gm-C amplifier combo. A class AB buffer is added to save static power while boost the maximum driving currents to data converter's 13pF input capacitance. Local autozeroing technique is applied to reduce low-frequency noise and offset. Amplified signals after the filters are sensed to control the tail current in the first stage gain amplifier. Noise and power tradeoff analysis of a typical OTA shows tail current can be utilized as the design variable. Therefore, a proposed power-adaptive sense amplifier reduces power consumption when no neural signal is present and increases power consumption to reduce input referred noise when neural signals exist. The fully integrated design measured 68dB to 0dB gain, 600 to 3kHz bandwidth, and occupied 0.21 mm2 area in IBM 0.18um CMOS process. The amplifier under 1.8V power supply consumes 16 uW when no neural signals exist and consumes 20uW when neural signals are present. The measured integrated input referred noise is 7uVrms within the band of interest. These sense amplifiers are also the first neural amplifiers implemented in 0.18 um CMOS process. This research demonstrates the superiority of open-loop autozeroing over chopping technique in power consumption performance. The auto-zeroing system's power consumption can be reduced 50 times at the expense of 6 time increase in noise compared to the chopping system's.Diagram. The architectural level of the second generation sense amplifier is shown in Fig. 4.2. This design still preserves the original idea such as fully differential 3-stage design while cascades another 1-order bandpass filter in the end toanbsp;...

Title:A Power Adaptive Low Power Low Noise Band-pass Auto-zeroing CMOS Amplifier for Biomedical Implants
Author: Chiu-Hsien Chan
Publisher:ProQuest - 2008

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